As an ASIC front to back design lead, you will lead the establishing & maintaining Synthesis, STA, Equivalency flows. You will be working with the ASIC design engineers to ensure high quality RTL, design constraints & Netlist preparation to hand off to a third-party physical design company. You will be responsible for ensuring the physical design partner receives Netlist & assist them with the design constraints issues as well as overseeing the floor planning, place & route & CDC placements. Once the Place & Route is complete, you will receive the post-layout Netlist to resolve the timing closure issues. PCIe/CXL switch chips have a high gate count & require a deep understanding of hierarchical Synthesis. Reponsibilities include:
- Build flows for methodologies incorporating front to back flow for Lint, Synthesis, prime time timing analysis, CDC & equivalency check.
- Writing scripts & establishing automation for Synthesis & Prime time tools.
- Provide support for ASIC tools and flows
- Work with 3rd party vendor with the Netlist hand-off & oversee the physical design & ensure a clean tape out.
- Full chip & block level timing constraints ensuring area & timing optimization
- Implement functional ECOs
- Monitoring DFT insertion for scan, memory Bist & Loopback tests mechanisms.
Benefits
Applicants must be authorized to work in the U.S.
Mike Vandenbergh is recruiting for this position and the positions below.
Email me to apply for this position
Employees will receive paid leave to the extent required by state or local law
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